The present invention relates generally to the field of memory devices and, in particular, to a circuit and method for a folded bit line memory cell with a vertical transistor and a trench capacitor.
Electronic systems typically store data during operation in a memory device. In recent years, the dynamic random access memory (DRAM) has become a popular data storage device for such systems. Basically, a DRAM is an integrated circuit that stores data in binary form (e.g., xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d) in a large number of cells. The data is stored in a cell as a charge on a capacitor located within the cell. Typically, a high logic level is approximately equal to the power supply voltage and a low logic level is approximately equal to ground.
The cells of a conventional DRAM are arranged in an array so that individual cells can be addressed and accessed. The array can be thought of as rows and columns of cells. Each row includes a word line that interconnects cells on the row with a common control signal. Similarly, each column includes a bit line that is coupled to at most one cell in each row. Thus, the word and bit lines can be controlled so as to individually access each cell of the array.
A memory array is typically implemented as an integrated circuit on a semiconductor substrate in one of a number of conventional layouts. One such layout is referred to as an xe2x80x9cfolded digit linexe2x80x9d architecture. In this architecture, sense amplifier circuits are provided at the edge of the array. The bit lines are paired in complementary pairs. Each complementary pair in the array feeds into a sense amplifier circuit. The sense amplifier circuit detects and amplifies differences in voltage on the complementary pair of bit lines as described in more detail below.
To read data out of a cell, the capacitor of a cell is accessed by selecting the word line associated with the cell. A complementary bit line that is paired with the bit line for the selected cell is equilibrated with the voltage on the bit line for the selected cell. The equilibration voltage is typically midway between the high and low logic levels. Thus, conventionally, the bit lines are equilibrated to one-half of the power supply voltage, VCC/2. When the word line is activated for the selected cell, the capacitor of the selected cell discharges the stored voltage onto the bit line, thus changing the voltage on the bit line.
The sense amplifier detects and amplifies the difference in voltage on the pair of bit lines. The sense amplifier typically includes two main components: an n-sense amplifier and a pxe2x88x92 sense amplifier. The n-sense amplifier includes a cross-coupled pair of n-channel transistors that drive the low bit line to ground. The pxe2x88x92sense amplifier includes a cross-coupled pair of pxe2x88x92channel transistors and is used to drive the high bit line to the power supply voltage.
An input/output device for the array, typically an n-channel transistor, passes the voltage on the bit line for the selected cell to an input/output line for communication to, for example, a processor of a computer or other electronic system associated with the DRAM. In a write operation, data is passed from the input/output lines to the bit lines by the input/output device of the array for storage on the capacitor in the selected cell.
Each of the components of a memory device are conventionally formed as part of an integrated circuit on a xe2x80x9cchipxe2x80x9d or wafer of semiconductor material. One of the limiting factors in increasing the capacity of a memory device is the amount of surface area of chip used to form each memory cell. In the industry terminology, the surface area required for a memory cell is characterized in terms of the minimum feature size, xe2x80x9cF,xe2x80x9d that is obtainable by the lithography technology used to form the memory cell. Conventionally, the memory cell is laid out with a transistor that includes first and second source/drain regions separated by a body or gate region that are disposed horizontally along a surface of the chip. When isolation between adjacent transistors is considered, the surface area required for such a transistor is generally 8F2 or 6F2.
Some researchers have proposed using a vertical transistor in the memory cell in order to reduce the surface area of the chip required for the cell. Each of these proposed memory cells, although smaller in size from conventional cells, fails to provide adequate operational characteristics when compared to more conventional structures. For example, U.S. Pat. No. 4,673,962 (the ""962 Patent) issued to Texas Instruments on Jun. 16, 1997. The ""962 Patent discloses the use of a thin poly-silicon field effect transistor (FET) in a memory cell. The poly-silicon FET is formed along a sidewall of a trench which runs vertically into a substrate. At a minimum, the poly-silicon FET includes a junction between poly-silicon channel 58 and the bit line 20 as shown in FIG. 3 of the ""962 Patent. Unfortunately, this junction is prone to charge leakage and thus the poly-silicon FET may have inadequate operational qualities to control the charge on the storage capacitor. Other known disadvantages of such thin film poly-silicon devices may also hamper the operation of the proposed cell.
Other researchers have proposed use of a xe2x80x9csurrounding gate transistorxe2x80x9d in which a gate or word line completely surrounds a vertical transistor. See, e.g., Impact of a Vertical "PHgr"-shape transistor (V"PHgr"T) Cell for 1 Gbit DRAM and Beyond, IEEE Trans. On Elec. Devices, Vol 42, No.12, December, 1995, pp. 2117-2123. Unfortunately, these devices suffer from problems with access speed due to high gate capacitance caused by the increased surface area of the gate which slows down the rise time of the word lines. Other vertical transistor cells include a contact between the pass transistor and a poly-silicon plate in the trench Such vertical transistor cells are difficult to implement due to the contact and should produce a low yield.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for realizable memory cell that uses less surface area than conventional memory cells.
The above mentioned problems with memory cells and other problems are addressed by the present invention and which will be understood by reading and studying the following specification. A memory cell is described which includes a vertical transistor and trench capacitor.
In particular, an illustrative embodiment of the present invention includes a memory cell for a memory array with a folded bit line configuration. The memory cell includes an access transistor that is formed in a pillar of single crystal semiconductor material. The access transistor has first and second sources/drain regions and a body region that are vertically aligned. The access transistor also includes a gate that is coupled to a wordline disposed adjacent to the body region of the access transistor. A passing wordline is separated from the gate by an insulator for coupling to other memory cells adjacent to the memory cell. A trench capacitor is also included. The trench capacitor includes a first plate that is formed integral with the first source/drain region of the access transistor and a second plate that is disposed adjacent to the first plate and separated from the first plate by a gate oxide. In another embodiment, the second plate of the trench capacitor surrounds the second source/drain region. In another embodiment, an ohmic contact is included to couple the second plate to a layer of semiconductor material.
In another embodiment, a memory device is provided. The memory device includes an array of memory cells. Each memory cell includes a vertical access transistor that is formed of a single crystalline semiconductor pillar that extends outwardly from a substrate. The semiconductor pillar includes a body and first and second source/drain regions. A gate is disposed adjacent to a side of the pillar adjacent to the body region. The memory cell also includes a trench capacitor wherein a first plate of the trench capacitor is integral with the first source/drain region and a second plate of the trench capacitor is disposed adjacent to the first plate. The memory device also includes a number of bit lines that are each selectively coupled to a number of the memory cells at the second source/drain region of the access transistor. This forms columns of memory cells in a folded bit line configuration. Finally, the memory device also includes a number of wordlines. The wordlines are disposed substantially orthogonal to the bit lines in trenches between rows of the memory cells. Each trench includes two wordlines. Each wordline is coupled to gates of alternate access transistors on opposite sides of the trench. In another embodiment, the pillars extend outward from a semiconductor portion of the substrate. In another embodiment, a surface area of the memory cell is four F2, wherein F is a minimum feature size. In another embodiment, a second plate of the trench capacitor surrounds the second source/drain region of the access transistor. In another embodiment, the second plate of the trench capacitor is maintained at approximately ground potential. In another embodiment, the pillar has a sub-micron width so as to allow substantially full depletion of the body region.
In another embodiment, a memory array is provided. The memory array includes a number of memory cells forming an array with a number of rows and columns. Each memory cell includes an access transistor with body and first and second source/drain regions formed vertically, outwardly from a substrate. A gate is disposed adjacent to a side of the transistor. The memory array includes a number of first isolation trenches that separate adjacent rows of memory cells. First and second wordlines are disposed in each of the first isolation trenches. The first and second wordlines are coupled to alternate gates on opposite sides of the trench. The memory array also includes a number of second isolation trenches, each substantially orthogonal to the first isolation trenches and intraposed between the adjacent memory cell.
In another embodiment, a method of fabricating a memory array is provided. A number of access transistors were formed wherein each access transistor is formed in a pillar of semiconductor material that extends outwardly from a substrate. The access transistor includes a first source/drain region, a body region and second source/drain region that are formed vertically. The method also includes forming a trench capacitor wherein a first plate of the trench capacitor is integral with the first source/drain region of the access transistor. Further, the method includes forming a number of wordlines in a number of trenches that separates adjacent rows of access transistors. Each trench includes two wordlines with the gate of each wordline interconnecting alternate access transistors on opposite sides of the trench. Finally, the method includes a number of bit lines that interconnect second source/drain regions of selected access transistors.
In another embodiment, a method of fabricating a memory is provided. The method begins with forming a first conductivity type first source/drain region layer on a substrate. A second conductivity type body region layer is formed on the first source/drain region layer. A first conductivity type second source/drain region layer is formed on the body region layer. Additionally, a plurality of substantially parallel column isolation trenches are formed extending through the second source/drain region layer, the body region layer and the first source/drain region layer. This provides column bars between the column isolation trenches. Further, a plurality of substantially parallel row isolation trenches are formed orthogonal to the column isolation trenches and extending to substantially the same depth as the column isolation trenches. This produces an array of vertical access transistors for the memory array. The row and column isolation trenches are filled with a conductive material to a level that does not exceed the lower level of the body region so as to provide a common plate for capacitors of the memory cells of the memory array. Two conductive wordlines are formed in each row isolation trench to selectively interconnect alternate access transistors on opposite sides of the row isolation trench. Finally, bit lines are formed to selectively interconnect the second source/drain regions of the access transistors on each column.